(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming thick oxide MOS transistors for electrostatic discharge protection in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Electrostatic discharge (ESD) robustness for CMOS technology has always been a difficult challenge. In larger feature size CMOS processes, thick oxide devices, such as the field oxide device (FOD) or the metal gate over field oxide device (MGFO), have been used to provide ESD protection for integrated circuit inputs. With the advent of sub-micron feature sizes, new approaches to ESD protection have become necessary.
Referring to FIG. 1, an input pad 10 is shown for a prior art CMOS integrated circuit. The input pad 10 in this application is connected to an inverter-buffer 18. To protect the transistors of the inverter-buffer 18 from ESD events, a field oxide device (FOD) 14 is fabricated on the circuit in the input path. The FOD transistor 14 is designed to perform several functions. First, if the FOD transistor 14 is an n-channel device, there is p-n diode between the substrate and the drain of the FOD. This will effectively clamp negative voltages to one diode drop below the substrate voltage. Second, and more importantly, the FOD device 14 is designed to shunt positive voltage spikes, such as during an ESD event, to the substrate while protecting the inverter-buffer 18.
Two features enable the FOD transistor 14 to protect against ESD events while not being destroyed in the process. First, the FOD transistor 14 is specially designed to have a large voltage threshold (V.sub.t). The FOD transistor 14 may be formed with either a polysilicon or metal gate. Unlike typical transistors, which have gate electrodes formed over very thin oxide, the FOD electrode is formed over a section of very thick field oxide. Since V.sub.t is proportional to the thickness of the gate oxide, V.sub.t for the FOD 14 is relatively large (15 V to 30 V) compared to that of the logic transistors of the inverter-buffer 18 (around 0.7 V). The large voltage threshold means that the FOD transistor is an open circuit for all expected input voltages excepting ESD events.
The second feature of the FOD transistor 14 is its performance during the ESD event. Under ESD stress conditions, the FOD behavior changes drastically from normal MOS operation. The conduction mechanism changes to a parasitic lateral bipolar device. Normal MOS channel conduction does not have the capability of carrying amps of current. The onset of bipolar action is determined by the avalanche breakdown of the n+ drain diffusion with the generation of electron-hole pairs. The generated electrons are swept across the drain towards the drain contact, adding to the drain current. The generated holes drift towards the substrate contact thereby giving rise to a substrate current similar to the base current of the bipolar transistor. As substrate current increases, the potential at the source-substrate junction increases to the point of forward-biasing this junction and causing electrons to be emitted into the substrate. When the electron current density from the source begins to contribute to the drain current, the parasitic bipolar transistor may be considered to be turned on. This is called snapback.
Once the lateral bipolar transistor turns on, the operating mechanism of the device is similar to that of an npn bipolar transistor. The drain voltage decreases. A negative resistance region is observed due to the availability of more carriers for multiplication until a minimum voltage is reached. A gate is not necessary for npn snapback to take place. However, in the FOD, the gate voltage can change the silicon surface potential and thereby reduce the source (emitter) barrier to turn on the npn device. The npn device turns on at a lower level to protect the thin gate oxide of the inverter-buffer 18.
Referring now to FIG. 2, a cross section of a prior art FOD transistor is shown. Field oxide regions 24 are formed in the substrate 20. Source junctions 32 and drain junctions 28 are formed in the substrate. The gate electrode 44 is formed by the metal layer 40 overlying field oxide region 24 between the source junction 32 and the drain junctions 28. The gate electrode 44 and the drain 48 are then connected to the input pad while the source 52 is connected to the circuit ground (VSS).
Sub-micron CMOS processes cause two problems for the prior art FOD approach. First, many new processes no longer have the field oxide layer formed by local oxidation of silicon (LOCOS). Shallow trench isolation (STI) has replaced LOCOS for isolation region definition. A controllable channel cannot be created under the STI structure. Even if a sub-micron process is not using STI, the shallowness of the junctions necessary to produce sub-micron transistors is a second problem. If very shallow source or drain junctions are used for the FOD, the threshold voltage is lowered. In addition, the device is easily damaged due to concentration of heating during the secondary breakdown event.
Several prior art approaches disclose methods to improve ESD performance of an integrated circuit device. U.S. Pat. No. 5,618,740 to Huang discloses a process to create CMOS outputs that have enhanced ESD resistance. CMOS output transistors do not receive the anti-punch through pocket implant as do core CMOS devices. The absence of the pocket junctions increases the ESD performance of the output transistors. U.S. Pat. No. 5,872,378 to Rose et al teaches an ESD protection network for non-volatile memory circuits. U.S. Pat. No. 5,929,493 to Wu discloses a process for forming CMOS transistors with self-aligned planarization twin well while using fewer masks. A boron blanket implant is included that will increase the threshold of the field oxide device.